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Can I use GPIO35, GPIO36 and GPIO37?

Applies to: ESP32-S3-DevKitC-1 official boards.

The question

“GPIO35/36/37 are in the pin table. Can I use them, or are they forbidden?”

Neither. The official answer is a condition on the module, quoted here verbatim from the guide:

For boards with Octal SPI flash/PSRAM memory embedded ESP32-S3-WROOM-1/1U modules, and boards with ESP32-S3-WROOM-2 modules, the pins GPIO35, GPIO36 and GPIO37 are used for the internal communication between ESP32-S3 and SPI flash/PSRAM memory, thus not available for external use.

So the same three header pins are ordinary GPIO on one board and wired to internal memory on another. A tutorial that says “never use 35-37” is describing only one of the two cases.

The decision table

Your board carriesInternal storage uses 35-37?GPIO35/36/37
WROOM-1 or WROOM-1U, without Octal SPI flash/PSRAM (e.g. N8, N8R2 modules)NoUsable as normal GPIO
WROOM-1 or WROOM-1U with Octal SPI flash/PSRAMYesNot available — used for internal communication
Any WROOM-2 (DevKitC-1-N32R16V)Yes (module family uses Octal throughout)Not available

Header positions: GPIO37 = J3 contact 11, GPIO36 = J3 contact 12, GPIO35 = J3 contact 13 (v1.1 J3 table).

How to check your board

  1. Read the module family from the shield silkscreen (WROOM-1 / WROOM-1U / WROOM-2) — see Which ESP32-S3-DevKitC-1 do I have?.
  2. If it is a WROOM-2: the pins are internal. Done.
  3. If it is a WROOM-1/1U: check the module’s storage variant against the WROOM-1/1U datasheet ordering table (the module suffix on the shield, e.g. N8R2 vs R8V-class variants). Octal flash/PSRAM variants occupy the pins; Quad SPI or no-PSRAM variants leave them free.
  4. Cross-check with the board SKU from the ordering table: the EOL N8/N8R2 boards match the “usable” row; R8 and N32R16V boards ship Octal PSRAM and match the “not available” row.

What happens if you use them anyway

On boards where the pins serve internal memory, attaching external circuitry to J3-11/12/13 interferes with the SPI lines between the ESP32-S3 and its flash/PSRAM — the module can fail to boot or crash at random, and the external circuit gets driven by SPI traffic. If a sketch that only toggles “harmless” pins behaves erratically, check what is wired to 35-37 first.

What this page cannot tell you

  • A software-side query that reports your module’s memory topology is not documented in the pinned guide. The reliable check is the silkscreen plus datasheet path above.
  • The exact per-SKU module suffix for the R8 boards is not spelled out in the board ordering table (it lists them as plain WROOM-1/1U) — hence the datasheet check in step 3.

Sources