RP2350

Type: chip · Vendor: raspberrypi

Raspberry Pi RP2350 microcontroller: dual-core Arm Cortex-M33 or dual-core Hazard3 RISC-V (software-selectable) up to 150 MHz, 520 kB SRAM, three PIO blocks, HSTX and a security suite. GPIO count and ADC channels depend on the package variant (A: 30 GPIO / 4 channels, B: 48 / 8).

RP2350 is Raspberry Pi’s second-generation microcontroller: a software-selectable dual-core Arm Cortex-M33 or dual-core Hazard3 RISC-V CPU at up to 150 MHz, 520 kB of on-chip SRAM, three PIO blocks, an HSTX high-speed output peripheral and a security architecture (TrustZone, signed boot, TRNG; in RISC-V mode some security features and the double-precision floating-point accelerator are unavailable). Whether it carries on-chip flash depends on the variant: RP2350A/B have none, RP2354A/B include 2 MB stacked flash.

Start from a board: Raspberry Pi Pico 2. Official docs: RP2350 chip overview.

Processing — dual Cortex-M33 or Hazard3 RISC-V, software-selectable, up to 150 MHz.
Memory — 520 kB SRAM; external QSPI flash / PSRAM via QMI, or 2 MB stacked flash on RP2354 variants.
I/O — three PIO blocks, HSTX for high-speed output, USB 1.1 host/device.

Capabilities — what the chip provides

Each row is one capability: the official wording, what it means in development, and the source. Variant-dependent numbers say so in their own row.

Capability	What it is · what it means for development	Source
Dual Cortex-M33 or Hazard3 RISC-V @ up to 150 MHz	“A choice of … Dual-core Arm Cortex-M33 / Dual-core Hazard3 RISC-V processor … at up to 150 MHz” (official wording). Software-selectable architecture — one chip, two instruction sets.	RP chip docs
520 kB on-chip SRAM, ten banks	“520 kB of on-chip SRAM in ten independent banks” (official wording). Double the RP2040's SRAM.	RP chip docs
External QSPI flash / PSRAM via QMI; variant with 2 MB stacked flash	“Run code directly from external flash … connect to external PSRAM through the QMI interface … RP2354A and RP2354B include 2 MB of stacked flash” (official wording). Unlike RP2040, some RP235x variants carry on-chip flash — the variant decides.	RP chip docs
4- or 8-channel ADC (variant) + temperature sensor	“Depending on variant, 4-channel or 8-channel ADC with internal temperature sensor, 500 kS/s, and 12-bit conversion” (official wording). Channel count depends on the chip variant (A vs B packaging).	RP chip docs
Three PIO blocks, twelve state machines	“three PIO blocks, each with four state machines (twelve in total)” (official wording). One more block than RP2040.	RP chip docs
2 UART / 2 SPI / 2 I2C / 16-24 PWM (variant) / USB 1.1 / HSTX	“Two UARTs … Two SPI … Two I2C … 16 or 24 PWM channels … A USB 1.1 controller and PHY … An HSTX peripheral for high-speed digital output” (official wording). HSTX drives high-speed digital output such as video; PWM channel count is variant-dependent.	RP chip docs
TrustZone / signed boot / OTP / SHA-256 / TRNG	“Security architecture built around Arm TrustZone … Signed boot support … OTP memory … SHA-256 acceleration … hardware TRNG” (official wording, abridged). A security feature set RP2040 does not have. In RISC-V mode some security features and the double-precision floating-point accelerator are unavailable (Architecture switching note); the affected subset is not enumerated here.	RP chip docs

Before you rely on a capability — scope and limits

Variants decide hardware facts. The number of ADC channels (4 on A variants, 8 on B; 12-bit conversion either way), PWM channels (16/24) and on-chip flash (none vs 2 MB stacked) differ between variants — identify the exact part before counting on them.
Flash is usually external. Like the RP2040, RP2350A/B run code from external QSPI flash the board provides; RP2354A/B are the stacked-flash exceptions.
PSRAM support is a chip feature, board wiring decides reality. QMI can talk to external PSRAM; whether your board exposes memory expansion is a board fact.
PIO is not the fixed peripherals. Same distinction as RP2040 — see the bus guide.
Security features are only as strong as your boot configuration. Signed boot, OTP and encryption need a deliberate key strategy; this page does not guide that process.
RISC-V mode leaves out part of the security suite and the double-precision FPU accelerator. The official Architecture switching note states that all chip features are available in RISC-V mode apart from some security features and the double-precision floating-point accelerator; which security features are affected is not enumerated here.

Boards built on the RP2350

Pinouts, revisions and connectors live on the board pages.

Boards using this chip

Raspberry Pi Pico 2

Start developing

MicroPython / C SDK — the Pico getting-started guide applies to the Pico 2 as well; BOOTSEL drag-and-drop works the same way.
Coming from an original Pico? Read Pico vs Pico 2 — official compatibility statement and the real differences.

Common questions this site answers

Pico vs Pico 2 — which board carries this chip, and what the W/H suffixes mean.
Getting started with the Pico — first flash and language choice, valid for both generations.
The board is not detected over USB — the BOOTSEL drive chain.
3.3 V and 5 V on the Pico — power rails and the ADC diode rule on Pico-series boards.

Sources and evidence

Chip capabilities — the table cites the RP2350 chip overview, features section, retrieved 2026-11-09.
Board facts — the Pico 2 page carries its own datasheet-sourced records.

Also known as: rp2350, RP2350.