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Raspberry Pi Pico

Type: board · Vendor: raspberry · Chip: RP2040

RP2040 microcontroller board with 2 MB flash, 40-pin 2.54 mm castellated/through-hole DIP format (51 x 21 mm), micro-USB B for power/data and drag-and-drop mass-storage flashing, 3-pin SWD pads at the bottom edge. No module layer: the RP2040 chip is soldered directly on the board.

The Raspberry Pi Pico is an RP2040 microcontroller board with 2 MB of on-board flash, a micro-USB B port for power, data and drag-and-drop flashing, and a 40-pin 2.54 mm castellated/through-hole DIP footprint (51 x 21 mm) usable on a breadboard or as a surface-mount module. This page renders the MCUID data record: the complete J1/J2 header mapping, the GPIOs consumed by internal board functions, and every published field tied to a fixed official source.

Start developing

  • Bring-up — the first-flash guide covers ports, cables and the first blink step by step.
  • Chip capabilities and limits — the RP2040 chip page separates what the chip provides from what this board wires up.

Common questions this site answers

Also known as: raspberry pi pico, rpi pico, pico 1.

No module layer

Unlike Espressif evaluation boards, the Pico has no module layer: the RP2040 chip, flash (Winbond W25Q16JV) and power circuitry are soldered directly on the board. The compatible-modules list below is intentionally empty — we do not invent a module record for a board that has none.

GPIOs used by internal board functions

The datasheet’s pinout section lists four GPIOs that the board design itself consumes:

  • GP25 — connected to the user LED (a single-color LED, not an addressable RGB LED)
  • GP24 — VBUS sense (high when USB power is present)
  • GP23 — SMPS power-save control (drive high for PWM mode / lower 3V3 ripple at light loads)
  • GP29 — VSYS monitor in ADC mode (ADC3, measures VSYS/3)

Unlike GP0–GP22 and GP26–GP28, these four GPIOs are not brought out on the J1/J2 header — the board routes them to the LED, the SMPS, VBUS and the VSYS divider, and the 40-pin contact table reflects exactly that. The claim table pins each one to its datasheet wording.

Flashing: BOOTSEL and UF2

Hold BOOTSEL while powering the board (e.g. while plugging in USB) and it enumerates as a USB mass-storage device; drag a .uf2 file onto it to reprogram the flash. The USB boot code lives in on-chip ROM and cannot be accidentally overwritten. The 3-pin SWD pads at the bottom edge (SWDIO, GND, SWCLK — no power pin) offer the debug alternative.

ADC pins: the reverse-diode limit

The ADC-capable pins GP26-GP28 (and GP29) have an internal reverse diode to the 3V3 rail: never exceed 3V3 + ~300 mV on them, and do not drive them while the board is unpowered — current leaks through the diode into the 3V3 rail. Normal digital GPIOs 0-25 do not have this diode — a difference in input structure, not a 5 V tolerance claim; per-pin absolute maximums remain a datasheet matter.

Default UART/I2C/SPI pins

The pico-sdk board header (tag 2.3.1) defines the software defaults — a pin-function convention, not a hardware restriction:

FunctionPinPhysical position
UART0 TX / RXGP0 / GP1J1 pin 1 / 2
I2C0 SDA / SCLGP4 / GP5J1 pin 6 / 7
SPI0 RX (MISO)GP16J2 pin 21
SPI0 CSnGP17J2 pin 22
SPI0 SCKGP18J2 pin 24
SPI0 TX (MOSI)GP19J2 pin 25

Related board

The Raspberry Pi Pico 2 keeps the same pinout and board layout with an RP2350: officially stated hardware and software compatibility, double the flash and SRAM.

2D pinout

No revision selected — pick a revision above to read its documented summary. Revision-independent facts (including the onboard LED GPIO, where published) are stated in the published-fields table regardless of selection.

Datasheet figure titles identify the current production board as 'Raspberry Pi Pico Rev3'. The datasheet release history tracks the document, not PCB revisions, so no per-revision change table is published for the board. · Pico datasheet

Raspberry Pi PicoJ1 (left header, physical pins 1-20) contact 1: GP0 (I/O) — GPIO0 (UART0 TX per SDK board header)GP0J1 (left header, physical pins 1-20) contact 2: GP1 (I/O) — GPIO1 (UART0 RX per SDK board header)GP1J1 (left header, physical pins 1-20) contact 3: GND (G) — GroundGNDJ1 (left header, physical pins 1-20) contact 4: GP2 (I/O) — GPIO2GP2J1 (left header, physical pins 1-20) contact 5: GP3 (I/O) — GPIO3GP3J1 (left header, physical pins 1-20) contact 6: GP4 (I/O) — GPIO4 (I2C0 SDA per SDK board header)GP4J1 (left header, physical pins 1-20) contact 7: GP5 (I/O) — GPIO5 (I2C0 SCL per SDK board header)GP5J1 (left header, physical pins 1-20) contact 8: GND (G) — GroundGNDJ1 (left header, physical pins 1-20) contact 9: GP6 (I/O) — GPIO6GP6J1 (left header, physical pins 1-20) contact 10: GP7 (I/O) — GPIO7GP7J1 (left header, physical pins 1-20) contact 11: GP8 (I/O) — GPIO8GP8J1 (left header, physical pins 1-20) contact 12: GP9 (I/O) — GPIO9GP9J1 (left header, physical pins 1-20) contact 13: GND (G) — GroundGNDJ1 (left header, physical pins 1-20) contact 14: GP10 (I/O) — GPIO10GP10J1 (left header, physical pins 1-20) contact 15: GP11 (I/O) — GPIO11GP11J1 (left header, physical pins 1-20) contact 16: GP12 (I/O) — GPIO12GP12J1 (left header, physical pins 1-20) contact 17: GP13 (I/O) — GPIO13GP13J1 (left header, physical pins 1-20) contact 18: GND (G) — GroundGNDJ1 (left header, physical pins 1-20) contact 19: GP14 (I/O) — GPIO14GP14J1 (left header, physical pins 1-20) contact 20: GP15 (I/O) — GPIO15GP15J1 (left header, physical pins 1-20)J2 (right header, physical pins 21-40) contact 21: GP16 (I/O) — GPIO16 (SPI0 RX / MISO per SDK board header)GP16J2 (right header, physical pins 21-40) contact 22: GP17 (I/O) — GPIO17 (SPI0 CSn per SDK board header)GP17J2 (right header, physical pins 21-40) contact 23: GND (G) — GroundGNDJ2 (right header, physical pins 21-40) contact 24: GP18 (I/O) — GPIO18 (SPI0 SCK per SDK board header)GP18J2 (right header, physical pins 21-40) contact 25: GP19 (I/O) — GPIO19 (SPI0 TX / MOSI per SDK board header)GP19J2 (right header, physical pins 21-40) contact 26: GP20 (I/O) — GPIO20GP20J2 (right header, physical pins 21-40) contact 27: GP21 (I/O) — GPIO21GP21J2 (right header, physical pins 21-40) contact 28: GND (G) — GroundGNDJ2 (right header, physical pins 21-40) contact 29: GP22 (I/O) — GPIO22GP22J2 (right header, physical pins 21-40) contact 30: RUN (I) — RP2040 enable; internal ~50 kOhm pull-up to 3.3 V, short low to resetRUNJ2 (right header, physical pins 21-40) contact 31: GP26 (I/O) — GPIO26 / ADC0GP26J2 (right header, physical pins 21-40) contact 32: GP27 (I/O) — GPIO27 / ADC1GP27J2 (right header, physical pins 21-40) contact 33: AGND (G) — Analog ground reference for GPIO26-29 (separate analog ground plane)AGNDJ2 (right header, physical pins 21-40) contact 34: GP28 (I/O) — GPIO28 / ADC2GP28J2 (right header, physical pins 21-40) contact 35: ADC_VREF (P) — ADC power supply/reference, 3.3 V filtered on-board; can be driven by an external referenceADC_VREFJ2 (right header, physical pins 21-40) contact 36: 3V3 (P) — 3.3 V output from on-board SMPS; keep external load below 300 mA3V3J2 (right header, physical pins 21-40) contact 37: 3V3_EN (I) — SMPS enable, pulled up to VSYS via 100 kOhm; short low to disable 3.3 V3V3_ENJ2 (right header, physical pins 21-40) contact 38: GND (G) — GroundGNDJ2 (right header, physical pins 21-40) contact 39: VSYS (P) — Main system input voltage, 1.8 V to 5.5 VVSYSJ2 (right header, physical pins 21-40) contact 40: VBUS (P) — Micro-USB input voltage, nominally 5 V (0 V when USB unpowered)VBUSJ2 (right header, physical pins 21-40)

power · ground · GPIO / signal · GPIO occupied by internal flash/PSRAM, either on this board design or on some compatible modules (see the exact condition on the linked claim)

Every pin block is a link: click or Tab + Enter to jump to its row below; LED pins lead to the revision-scoped claim with its fixed source. The selected revision and last pin are restorable from the URL hash (e.g. #rev=v1.1/pin=J3-10); an unknown revision value is reported, never defaulted.

J1 (left header, physical pins 1-20) contacts

Contact names and functions follow the official Pico pinout figure (Raspberry Pi documentation repository, same board revision as the datasheet) cross-checked against the datasheet text: the seven non-GPIO header positions named there (VBUS, VSYS, 3V3_EN, 3V3, ADC_VREF, AGND, RUN) match this table. Type letters are an editorial summary (I/O = 3.3 V GPIO, G = ground, P = power); the datasheet itself does not publish a typed pin table. · Source: Pico datasheet

No.NameTypeGPIOFunction (official)
1GP0I/O0GPIO0 (UART0 TX per SDK board header)
2GP1I/O1GPIO1 (UART0 RX per SDK board header)
3GNDG—Ground
4GP2I/O2GPIO2
5GP3I/O3GPIO3
6GP4I/O4GPIO4 (I2C0 SDA per SDK board header)
7GP5I/O5GPIO5 (I2C0 SCL per SDK board header)
8GNDG—Ground
9GP6I/O6GPIO6
10GP7I/O7GPIO7
11GP8I/O8GPIO8
12GP9I/O9GPIO9
13GNDG—Ground
14GP10I/O10GPIO10
15GP11I/O11GPIO11
16GP12I/O12GPIO12
17GP13I/O13GPIO13
18GNDG—Ground
19GP14I/O14GPIO14
20GP15I/O15GPIO15

J2 (right header, physical pins 21-40) contacts

Same provenance as J1. The ADC-capable pins GP26-28 have an internal reverse diode to the 3V3 rail: the input voltage must not exceed 3V3 plus about 300 mV, and driving them while the board is unpowered leaks current into the 3V3 rail (datasheet section 5.2). · Source: Pico datasheet

No.NameTypeGPIOFunction (official)
21GP16I/O16GPIO16 (SPI0 RX / MISO per SDK board header)
22GP17I/O17GPIO17 (SPI0 CSn per SDK board header)
23GNDG—Ground
24GP18I/O18GPIO18 (SPI0 SCK per SDK board header)
25GP19I/O19GPIO19 (SPI0 TX / MOSI per SDK board header)
26GP20I/O20GPIO20
27GP21I/O21GPIO21
28GNDG—Ground
29GP22I/O22GPIO22
30RUNI—RP2040 enable; internal ~50 kOhm pull-up to 3.3 V, short low to reset
31GP26I/O26GPIO26 / ADC0
32GP27I/O27GPIO27 / ADC1
33AGNDG—Analog ground reference for GPIO26-29 (separate analog ground plane)
34GP28I/O28GPIO28 / ADC2
35ADC_VREFP—ADC power supply/reference, 3.3 V filtered on-board; can be driven by an external reference
363V3P—3.3 V output from on-board SMPS; keep external load below 300 mA
373V3_ENI—SMPS enable, pulled up to VSYS via 100 kOhm; short low to disable 3.3 V
38GNDG—Ground
39VSYSP—Main system input voltage, 1.8 V to 5.5 V
40VBUSP—Micro-USB input voltage, nominally 5 V (0 V when USB unpowered)

Ordering variants

Part numberModuleFlashPSRAMAntennaStatus
No ordering variants recorded for this board yet.

Published fields

FieldValueApplies toStatusSourceNotes
onboard_led.gpio25All revisionsverified · cc40 · 2026-11-08Pico datasheetDatasheet: 'GPIO25 OP Connected to user LED'. A single-color LED, NOT an addressable RGB LED (the pico-sdk board header defines PICO_DEFAULT_LED_PIN 25 and has no WS2812 pin).
vbus_sense.gpio24All revisionsverified · cc40 · 2026-11-08Pico datasheet'GPIO24 IP VBUS sense - high if VBUS is present, else low'.
smps_power_save.gpio23All revisionsverified · cc40 · 2026-11-08Pico datasheet'GPIO23 OP Controls the on-board SMPS Power Save pin'. Per the pico-sdk board header, drive high to force the power supply into PWM mode (lower ripple on 3V3 at light loads).
vsys_monitor.gpio29All revisionsverified · cc40 · 2026-11-08Pico datasheet'GPIO29 IP Used in ADC mode (ADC3) to measure VSYS/3'.
power.vsys_range1.8 V to 5.5 VAll revisionsverified · cc40 · 2026-11-08Pico datasheetVSYS feeds the on-board buck-boost SMPS that generates 3.3 V; the 3V3 pin can power external circuitry but the load should stay below 300 mA.
flash.size2 MBAll revisionsverified · cc40 · 2026-11-08Pico datasheet'RP2040 microcontroller with 2 MB Flash'; external circuitry uses a Winbond W25Q16JV quad-SPI flash chip.
swd.connector3-pin castellated through-hole pads (SWDIO, GND, SWCLK), no power pinAll revisionsverified · cc40 · 2026-11-08Pico docsDebug connector table: Pico and Pico 2 carry three castellated through-hole pads on the bottom edge; the connector carries SWDIO, GND and SWCLK only, the board must be powered separately over USB or VSYS.
usb.flash_modehold BOOTSEL at power-up, then drag-and-drop a .uf2 file onto the exposed USB mass-storage driveAll revisionsverified · cc40 · 2026-11-08Pico datasheetDatasheet section 1: 'Reprogramming the Pico Flash can be done using USB (simply drag and drop a file onto the Pico which appears as a mass storage device)'. Section 4.1 details the flow; the boot code lives in on-chip ROM, so it cannot be accidentally overwritten.

Compatible modules

  • No module layer: the chip is soldered directly on this board (see the chip link in the header above). We do not invent a module record for a board that has none.